A. Field of the Invention
The invention relates to semiconductor device and processes of manufacture. More particularly, the invention relates to field effect transistors having reduced parasitic capacitance and processes of manufacture therefor.
B. Description of the Prior Art
Parasitic capacitance exists in insulated gate field effect transistors where the gate electrode overlaps the source and drain diffusions. Circuit performance of such devices in terms of switching speed, rise and fall times is decreased relative to optimum performance. Normally, self aligned gate processes are employed to reduce the gate electrode overlap of the source and drain regions. In a self aligned gate process, the gate region is specified before the source/drain diffusions are performed. Self aligned processes remove the portion of the overlap region which is designed into conventional metal gate processes to compensate for the misregistration of the different mask levels. The small amount of residual overlap in self aligned processes is comparatively minor and does not significantly impact circuit performance. Self aligned gate processes, however, require polysilicon or silicon nitride or other materials to carry out the process. Etching of these materials is complicated and difficult to control resulting in lower yields for self aligned processes than for metal gate processes.
A metal gate process that reduces overlap capacitance and does not introduce new process steps, materials or etchants in metal gate process will significantly contribute to improve insulated gate filed effect transistors. One solution to achieve this result is to increase the insulation thickness over the source/drain regions and minimize the length of the gate overlap. Insulation thickness over the diffused regions can be maximized relative to the undiffused region due to the differential oxidation rates there between. In a previously filed application, Ser. No. 411,518 filed Oct. 31, 1973, now U.S. Pat. No. 3,899,372 issued Aug. 12, 1975 assigned to the present assignee, the differential oxidation rates of these regions are utilized to achieve a substantially planar insulating level for a metal gate transistor. Adopting the principals of the previously filed application, a metal gate process can be realized which increases diffused insulation thickness and reduces gate overlap.
An object of the present invention is a semiconductor device having improved performance by reduced parasitic capacitance.
Another object is a field effect transistor having reduced gate overlap capacitance and a substantially planar field and diffusion insulating layers.
Another object of the invention is a field effect transistor having reduced overlap capacitance.
Another object of the invention is a field effect transistor having increased gate overlap insulating thickness.
Another object of the invention is a process of fabricating a semiconductor device having reduced parasitic capacitance.
Another object of the invention is a process of fabricating a field effect transistor that is compatible with conventional metal gate processes to achieve increased gate overlap insulating thickness and reduced length of gate overlap of the diffused regions.